Semiconductor integrated circuit devices commonly employ capacitors that are integrated directly into the devices. Such integrated capacitors include first and second electrodes that are spaced apart by a dielectric layer. In integrated devices, capacitors have been formed in a number of different configurations, including MOS (metal-oxide-semiconductor) capacitors, PN junction capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, and MIM (metal insulator-metal) capacitors, each being characterized by the types of materials used to form the electrodes and dielectric layer.
The MOS and PIP capacitor types employ a polycrystalline semiconductor layer or single-crystal semiconductor layer as an electrode of the capacitor, and the PN junction capacitor types employ a doped single-crystal semiconductor as a bottom electrode. It is well understood that such polycrystalline semiconductor or single-crystal semiconductor materials exhibit a resistivity that is higher than that of metal. In addition, when a bias voltage is applied to a capacitor electrode formed of a polycrystalline semiconductor or single-crystal semiconductor material, a depletion region is generated, causing the applied bias voltage to become unstable, in turn causing an undesirable variation in the capacitance value of the capacitor. Variation in the capacitance value of a capacitor makes the capacitor highly dependent on the frequency of the signal applied to the capacitor. To improve the signal-to-noise ratio (SNR) in CMOS logic analog devices, such as analog-to-digital converters, and the like, it is desirable to decrease the voltage coefficient of capacitance, or VCC, of a CMOS analog capacitor. A decrease in VCC means that the change in capacitance is relatively low in response to a variation in applied voltage. The VCC value is characterized by:
            V      ⁢                          ⁢      C      ⁢                          ⁢      C        =                  1                  C          0                    ⁢              (                              ⅆ            C                                ⅆ            V                          )              ,where C0 is the nominal capacitance of the device, and where (dC/dV) is the variation of capacitance in response to applied voltage.
MIM capacitors, on the other hand, employ metal materials for forming the capacitor electrodes. As a result, the capacitor electrodes have lower resistivity. Lower resistivity leads to a more stable capacitance value in the resulting capacitor, in turn leading to reduced frequency dependence. When a bias voltage is applied to a capacitor electrode formed of metal, little or no depletion region is generated, and therefore, it is possible to achieve a stable capacitance value, despite variation in applied voltage.
With such stable capacitance properties, MIM capacitors enjoy widespread application in integrated devices, such as analog devices, system-on-a-chip (SoC) devices, and mixed mode signal applications. For example, such MIM capacitors are readily applied to CMOS image sensor s(CIS), LCD driver ICs (LDI), RF filter devices, and the like.
A conventional PIP capacitor includes first and second electrodes formed of polysilicon that are separated by an insulating capacitor dielectric layer. Fabrication of a PIP capacitor is relatively simple, since only a single additional photomask is required for forming the capacitor components. In addition, PIP capacitors are generally formed on a lower level of the device, and as a result, enjoy enhanced wiring characteristics, since a wide routing area for metal interconnection is available, since metal interconnection lines on the upper-level layers, such as the metal-1 and metal-2 layers, can be routed directly over the position of the PIP capacitor, without interfering with the capacitor. However, as stated above, such PIP capacitors suffer from high capacitance variation, as the polysilicon electrode characteristically includes a depletion region. The depletion region prevents applicability of the PIP capacitor to formation of a high value performance capacitor, having a high capacitance value, and a low VCC value.
In contrast, a conventional MIM capacitor offers high-performance operation, but interferes with upper-level wiring because MIM capacitors have large top and bottom electrodes that are formed in the metal wiring layers, such as the metal-1, metal-2 and upper-level layers. Therefore, the electrodes occupy space that would otherwise be occupied by interconnection lines in the metal layers. In addition, at least two additional photolithography masks are generally required for forming an integrated MIM capacitor to define top and bottom plates, respectively, in order to complete fabrication of the device, complicating fabrication of the device.